Phase modulators have proved useful for a number of technical applications. Finisar Corporation, for example, has released a line of telecommunications products based in part on the use of a liquid crystal on silicon microdisplay configured as a phase modulator. Other companies have proposed similar devices configured to operate as optical tweezers and spatial beam shapers.
The application of phase modulators to optical communications systems has long been studied. Numerous conferences sponsored by SPIE (The International Society for Optical Engineering), OSA (The Optical Society) and other optics industry trade groups and technical societies have explored the concepts of using phase modulators to accomplish free space interconnect between fiber optic lines. The addition of a reconfigurable phase modulator based on liquid crystal on silicon (LCOS) technology has been explored at some length. The use of a phase configured LCOS device as a wavelength selective switch (WSS) has been the topic of a number of papers. Of particular interest is the deployment of LCOS WSS devices in Reconfigurable Optical Add Drop Multiplexor (ROADM) switch units in metro and long haul Optical Transport System (OTS) fiber optic networks. ROADM units are important to these OTS because they enable a first fiber optic line to be routed to a second fiber optic line without the need to convert the incoming optical signal on the first fiber optic to an electrical signal and then back to an optical signal inserted into the second fiber optic line.
The range of wavelengths over which phase modulation is useful ranges from 400 nanometers to the upper end of the short infrared telecommunications wavelengths on the order of 1600 nanometers. Wavelengths outside the range are foreseeable. A given phase modulator may not need to cover the entire range described above and different liquid crystal cell configurations may prove an optimal approach. It should be noted that a single backplane and drive hardware configuration may be used with a variety of different liquid crystal cell configurations.
All potential uses are included within the scope of the present invention.
In this application the terms microdisplay, spatial light modulator, imager and panel are all understood to refer to a device capable of modulating light by altering the phase state of said light. The microdisplay may be a reflective or transmissive liquid crystal device, a MEMS (Micro-Electro Mechanical System) device, or another type device based on other modulation principles. In this application the term frame is used to denote an output frame containing all of the data required to phase modulate a beam of light. The output frame may be repeated a plurality of times before new input data is received.
FIG. 1 depicts one potential application of the present invention, a simplified diagram of a ROADM (Reconfigurable Optical Add Drop Multiplexer) 100. A ROADM is principally used as an optical inter-connect in long and medium haul fiber optic networking. A ROADM is an attractive to network developers for several reasons. A first advantage is that it allows the data being transmitted to remain in the optical domain by eliminating the need to down convert the incoming optical signal to an electrical signal so that it can then be up converted to an optical signal on an outgoing fiber optical line. A second advantage is that the ROADM can be reconfigured optical as network requirements evolve, whether the evolution is related to differences during the day or to fundamental changes in the network requirements.
As shown in FIG. 1, a ROADM 100 comprises fiber optic front end 130, cylindrical mirror 115, diffraction grating 120 and phase aligned spatial light modulator 125. Those of skill in the art of ROADMS will recognize that other components (not shown) may improve a ROADM over the example shown. See, for example, U.S. Pat. No. 7,397,980, Frisken, for further information. Telecommunications beam of light 110 exits a fiber optic line in front end 130 and is reflected by cylindrical mirror 115 to diffraction grating 120. Diffraction grating 120 reflects telecommunications beam of light 110 with every wavelength reflected at a different angle with close wavelengths at only slightly different angles. Diffracted beam of light 110 then is reflected again by cylindrical mirror 115 to phase-aligned spatial light modulator 125. Phase-aligned spatial light modulator 125 is configured with a set of data that configures the pixel array such that beams of light incident on a display of the spatial light modulator 125 are steered to a desired exit angle. The steered beam of light then reverses the original path and enters an outgoing fiber optic line in front end 130.
The range of wavelengths associated with fiber optic telecommunications has increased over time. Different channels are differentiated by wavelength, by polarization orientation, by pulse rate, and by other features, depending on the particular network design.
A common configuration for a liquid crystal on silicon microdisplay used as a phase modulator comprises a parallel aligned homogeneous non-twist nematic liquid crystal cell with the alignment angle set parallel to the polarization vector of the coherent illumination. In this configuration the LCOS microdisplay performs phase only modulation with only minimal amplitude modulation attributable to the effect manufacturing tolerances have throughout the system on the polarization state of light. Further information on the parallel aligned homogeneous non-twist liquid crystal may be found in “Characteristics of LCOS Phase-only spatial light modulator and its application,” Dai et al, Optics Communications Vol. 238, pp. 269-276, 2004, especially section 3.2. A second reference is “Introduction to Microdisplays,” Armitage et al, John Wiley & Sons, 2006, pp. 182-185.
When a microdisplay utilizing a nematic liquid crystal cell is pulse width modulated, there is a problem of phase stability. Because the drive is between a first drive voltage corresponding to a higher level of retardance and a second drive voltage corresponding to a lower level of retardance, it is necessary to have a scheme to achieve intermediate levels of retardance.
In the present case intermediate levels of retardance are achieved by insuring that the pulse width modulation scheme is configured to operate at a speed significantly higher than the time required for the liquid crystal material to respond directly to the modulation scheme. In this instance the liquid crystal material responds at a relatively slow rate to changes in modulation, thus acting as a low pass filter on the modulating waveform.
Some attention must be paid to the nature of the nematic liquid crystal material used in the liquid crystal device. There are many different liquid crystal materials available through various sources.
A first consideration is that the extent of lateral fields between adjacent pixels needs to be minimized to avoid misalignments in the liquid crystal cell there that will result in reflections in a spurious phase state. Means for minimizing lateral fields in liquid crystal displays are well known in the art. A first method is to insure that the cell gap between the pixels and the counter electrode is as small as possible. It is highly desirable to reduce this gap to a quarter of the pitch between adjacent pixels if possible, although the cell gap must be thick enough to enable the liquid crystal cell to provide the required range of retardance at the wavelengths of interest.
An additional means for minimizing cell gap is to use a liquid crystal with a high birefringence (Δn). Liquid crystal materials with a high birefringence suitable for use in phase aligned liquid crystal cells are well documented in the relevant literature. It is also certain that no single material simultaneously satisfies all possible requirements because some requirements conflict with other requirements. For example, it is desirable that the liquid crystal cell respond quickly to changes in the data pattern presented to it. It is also desirable that the liquid crystal cell smooth the pulse width modulation pattern applied to it. These two features conflict with one another. In the examples of the present application the assumption will be that the smoothing feature dominates over the response time for new all pulse width modulation patterns unless otherwise indicated.
The following table from Table 1 in “Studies of Liquid Crystal Response Time,” Wang, University of Central Florida, Doctoral Dissertation, 2005, shows a number of factors pertaining to a liquid crystal cell and their impact on the response time of a liquid crystal cell.
FactorsTriseTdecayViscosity (γ1) ↓↓↓Elastic constants (Kii) ↑↑↓Dielectric anisotropy (Δε) ↑↓↓Thickness (d) ↓↓↓Pretilt angle (θ0) ↓↑↓Anchoring energy (W) ↑↑↓Temperature (T) ↑↓↓Voltage (v) ↑↓↓
The terms Trise and Tdecay are related to the drive state of the liquid crystal cell with specific regard to the magnitude of the potential between a pixel mirror and the common electrode.
LC Mode →Normally BlackNormally White (parallelRetardance State ↓(VAN, etc.)aligned homogeneous, etc.)High RetardanceRise (Driven)Decay (Relaxed)Low RetardanceDecay (Relaxed)Rise (Driven)
Trise is associated with the state in which the pixel mirror cell is driven to a higher absolute voltage relative to the common plane (ITO) voltage while Tdecay is associated with the state in which the pixel mirror cell is driven to a lower absolute voltage difference relative to the common plane voltage. A normally black liquid crystal cell rises to its high retardance state in response to a higher absolute voltage difference between the pixel mirror and the counter electrode and decays or falls or relaxes to its low retardance state in response to a lower absolute voltage difference between the pixel mirror and the common plane. A normally white liquid crystal cell decays or falls to its high retardance state in response to a lower absolute voltage between the pixel mirror and the common plane and rises to its low retardance state in response to a higher absolute voltage between the pixel mirror and the common plane.
A higher rotational viscosity γ1 is associated with a higher rise and fall time, which is a desirable characteristic for a smooth response to a pulse width modulation sequence. Higher rotational viscosity is routinely associated with high birefringence (Δn) due to the molecular structure of the liquid crystal materials required to reach high birefringence.
The elastic constants K11, K22, and K33 quantify the tendency of a liquid crystal cell to return to its relaxed state when the driving field is reduced or removed as well as its resistance to deformation when the driving field is increased. The listed elastic constants correspond to splay, twist and bend respectively. In a parallel aligned homogeneous liquid crystal cell the splay elastic constant K11 is dominant. As K11 increases the time required to move to its driven state increases and the time required to move to its relaxed state decreases.
Thus the performance of a liquid crystal cell under driving conditions is a complex matter as is well known in the art. Ultimately a particular liquid crystal cell configuration must be tested to determine precisely how it performs in response to a particular driving condition.
FIGS. 2A and 2B show the general construction of a liquid crystal on silicon (LCOS) micro-display panel 200. A single pixel cell 205 includes a liquid crystal layer 230 between a transparent common electrode 242 formed on glass substrate 240, and a pixel electrode 250. Alignment layers (not shown) of a suitable material such as polyimide or silicon dioxide (SiO2) as is well known in the art, are interposed between transparent electrode 242 and liquid crystal layer 230 and between liquid crystal layer 230 and pixel electrode 250. A storage element 210 is coupled to the pixel electrode 250, and includes complementary data input terminals 212 and 214, a data output terminal 216, and a control terminal 218. The storage element 210 is responsive to a write signal placed on control terminal 218, reads complementary data signals asserted on a pair of bit lines (BPOS and BNEG) 220 and 222, and latches the data signal through the output terminal 216. Since the output terminal 216 is coupled to the pixel electrode 250, the data (i.e. high or low voltage) passed by the storage element 210 is imparted on pixel electrode 250. Pixel electrode 250 is preferably formed from a highly reflective polished aluminum. In the liquid crystal display panel 200, a pixel electrode 250 is provided for each pixel in the display. For example, in a Full High Definition display system conforming to the SMPTE 274M-2005 standard that requires an array of 1920×1080 pixels, there would be an individual pixel electrode 250 for each of the 2,073,600 pixels in the array. The transparent common electrode 242 is preferably formed from Indium Tin-Oxide (ITO) on glass substrate 240 by some suitable process such as sputtering. A voltage (VITO) is applied to transparent common electrode 242 through a common electrode terminal (not shown) and in conjunction with the voltage applied to each individual pixel electrode, determines the magnitude and polarity of the voltage across liquid crystal layer 230 within each pixel cell 205 in the display panel 200.
When incident polarized beam of light 260 is directed at pixel cell 205, passes through transparent common electrode 242 the polarization state of incident beam of light 260 is modified by the liquid crystal material 230. The manner in which the liquid crystal material 230 modifies the state of polarization of incident beam of light 260 is dependent on the orientation of the liquid crystal molecules within the path of the beam of light 260 which is in turn dependent on the RMS voltage applied across the liquid crystal between common electrode 242 and pixel electrode 250. For example, applying a certain voltage across the liquid crystal material 230 will reflect beam of light 262 but in a form wherein the polarization state of beam of light 262 is only identical to that of beam of light 260 when the molecules of liquid crystal layer 230 are oriented such that no change to the polarization state of beam of light 260 occurs. This is well known in the art. When reflected beam of light 262 possesses a polarization state differing from that of incident beam of light 260, thus encoding information onto the beam of light 262. a fraction of the incident polarized_light to be reflected back through the liquid crystal material and the transparent common electrode 240 in a modified polarization state that will pass through subsequent polarizing elements. After passing through the liquid crystal material 230, the incident light beam 260 is reflected by the pixel electrode 250 and back through the liquid crystal material 230. After reflected beam of light 262 passes through subsequent polarizing elements and is thereby analyzed, according to the term of art, the analyzed beam of light (not shown) is attenuated according to the specifics of the exact polarization state of reflected beam of light 262. The luminance of an exiting light beam 262 is thus dependent on the degree of polarization rotation imparted by the liquid crystal material 230, which is in turn dependent on the voltage applied across the liquid crystal material 230.
Storage element 210 is preferably formed from a CMOS transistor array in the form of a static random access memory (SRAM) cell, i.e., a latch, but may be formed from other known memory logic circuits. SRAM latches are well known in semiconductor design and manufacturing and provide the ability to store a data value, as long as power is applied to the circuit. Other control transistors may be incorporated into the memory chip as well. The physical size of a liquid crystal display panel utilizing pixel cells 205 is determined by a number of factors, including the pixel size, the array dimensions and the amount of border space required for row and column addressing circuits as well as bond pads and buffering circuitry. Pixel sizes in use today were deemed optically impossible late in the 1990s decade.
Since the transparent common electrode 242 and glass substrate 240 form a single common electrode, their physical size will substantially match the total physical size of the pixel cell array with some margins to permit external electrical contact with the ITO and space for gaskets and a fill hole to permit the device to be sealed after it is filled with liquid crystal (not shown).
In U.S. Pat. No. 8,421,828, hereinafter '828, applicant discloses a method for applying pulse width modulation to a digital display backplane. The modulation method uses different row spacings within a group of row write actions to form a template that can then be repeated by adjusting the start point of a subsequent application of the template while maintaining the same row spacing between members of the group. Because the row write actions are not always physically adjacent it is necessary to insure that the rows of the display are addressed using row address decoder means and not using a shift register write mechanism. A suitable row addressing scheme has long been known in the art of digital memory devices, including SRAM memories. A suitable implementation of a row address decoder circuit is disclosed in “Modern MOS Technology: Processes, Devices, and Design”, pp. 208-211, DeWitt G. Ong, McGraw-Hill, 1984.
FIG. 3A shows an electro-optical curve (EO-curve or liquid crystal response curve) for a typical phase only liquid crystal mode known as the parallel aligned ECB (electrically controlled birefringence) mode with optical compensation operated in the normally white (NW) mode from “Introduction to Microdisplays”, Armitage et al, FIG. 6.11, page 183. Three curves are presented for three different wavelengths of light. The parallel aligned ECB mode is ideal for a phase only spatial light modulator. Care should be taken to insure that the light to be phase modulated is substantially polarized and that the polarization vector is aligned with the front director of the liquid crystal cell. As illustrated in FIG. 3A, as the voltage applied to the liquid crystal increases, the degree of modification to the phase state of the reflected light is decreased. As a practical consideration the prime consideration for a phase modulator is not the degree of phase shift induced on the illumination beam but rather the relative phase induced on light reflected by each pixel mirrors. This is purely a function of the modulation induced by each pixel. At an RMS voltage that corresponds to the point of least retardance, the crystal components are aligned in an approximately vertical stack of liquid crystal molecules such that the phase of the reflected light is modified least compared to that of the incoming light source. As a result the concepts of high contrast and dark state so commonly used in display systems are less meaningful.
FIG. 3B depicts a response waveform 186 of a parallel aligned phase only liquid crystal mode device to square wave voltage waveform 185. Square wave voltage waveform 185 represents a typical waveform seen in a pulse width modulated display. Response waveform 186 is typical of parallel aligned liquid crystal mode devices in that the rise time to full retardance is slow (relaxation mode) and the fall time to lower retardance is fast (driven mode).
FIG. 4 shows a block diagram of a single pixel cell 305 of a display with the pixel circuit disclosed in U.S. Pat. No. 7,443,374. Pixel cell 305 comprises storage element 300, DC (direct current) balance control element 320, and inverter 340. DC balance control element 320 is preferably a CMOS based logic device that can selectively pass to another device one of several input voltages. Storage element 300 comprises complementary input terminals 302 and 304, respectively coupled to data lines (BPOS) 350 and (BNEG) 352. Storage element 300 also comprises complementary enable terminals 306 and 307 coupled to word line (WLINE) 356, and a pair of complementary data output terminals (SPOS) 308, and (SNEG) 310. In the present embodiment, storage element 300 is an SRAM latch, but those skilled in the art will understand that any storage element capable of receiving a data bit, storing the bit, and asserting the complementary states of the stored bit on complementary output terminals may be substituted for the SRAM latch storage element 300 described herein.
DC balance control element 320 comprises complementary data input terminals 324 and 326 which are coupled respectively to data output terminals (SPOS) 308 and (SNEG) 310 of storage element 300. DC balance control element 320 also comprises a first voltage supply terminal 328, and a second voltage supply terminal 330, which are coupled respectively to the third voltage supply terminal (VSWA_P) 376, and the fourth voltage supply terminal (VSWA_N) 378 of voltage controller 384 (See FIG. 7). DC balance control element 320 further includes a third voltage supply terminal 332, and a fourth voltage supply terminal 334, which are coupled respectively to the fifth voltage supply terminal (VSWB_P) 380, and the sixth voltage supply terminal (VSWA_N) 382 of voltage controller 384. (See FIG. 7) DC balance control element 320 further comprises data output terminal 322 that is coupled to data input terminal 348 of inverter 340.
A full explanation of the operation of DC balance control element 320 is found in U.S. Pat. No. 7,443,374, in FIG. 6, and the corresponding text at Col. 11, lines 32-51, as corrected. And in FIGS. 12A through 12F and the corresponding text at Col. 17, line 18, through Col. 18, line 9.
Inverter 340 includes first voltage supply terminal 342, and second voltage supply terminal 344, which are coupled respectively to first voltage supply terminal (V1) 372, and second voltage supply terminal (V0) 374 of voltage controller 384. Inverter 340 also comprises data input terminal 348 coupled to data output terminal 322 of DC balance control element 320, and pixel voltage output terminal (VPIX) 346 coupled to pixel mirror 354. Responsive to the voltage asserted on input terminal 348, inverter 340 asserts the correct voltage among V0 374 and V1 372 onto pixel mirror 354 through output terminal 346.
U.S. Pat. Nos. 6,005,558, 6,067,065, 7,379,043, 7,443,374, 7,468,717 and 8,040,311 disclose backplanes compatible with the modulation method of the present application. These patents are incorporated into the present application in their entireties by reference.
FIG. 5 depicts voltage and control logic for a display system 394 comprises an array of pixel cells 305 comprising a plurality of rows and columns, voltage controller 384, a processing unit 388, memory unit 386, and transparent common electrode 392. Transparent common electrode 392 overlays the entire array of pixel cells 305. In a preferred example, pixel cells 305 are formed on a silicon substrate or base material, and are overlaid with an array of pixel mirrors 354 (from FIG. 4), each single pixel mirror 354 forming a part of one of the pixel cells 305. Each pixel cell 305 comprises the circuit elements disclosed in FIG. 4. A substantially uniform layer of liquid crystal material is located in between the array of pixel mirrors 354 and the transparent common electrode 392. Transparent common electrode 392 is preferably formed by a transparent conductive material such as Indium Tin-Oxide (ITO) coated onto a glass substrate as previously disclosed in FIGS. 2A and 2B, items 242 and 240, respectively. Memory unit 386 is a computer readable medium including programmed data and commands. The memory unit 386 is capable of directing processing unit 388 to implement various voltage modulation and other control schemes. Processing unit 388 receives data and commands from memory unit 386, via memory bus 387, provides internal voltage control signals, via voltage control bus 390, to voltage controller 384, and provides data signals (i.e. image data into the pixel array) via data control bus 385 (connection not shown). Voltage controller 384, memory unit 386, and processing unit 388 may be separate units or alternative may form part of a larger circuit assembly in a larger integrated circuit or circuit board assembly. Memory unit 386 may comprise both operating RAM and nonvolatile memory such as an SPI (Serial Peripheral Interface) memory. (Not shown)
Responsive to control signals received from processing unit 388, via voltage control bus 390, voltage controller 384 provides predetermined voltages to each pixel cells 305 via a first voltage supply terminal (V1) 372, a second voltage supply terminal (V0) 374, a third (logic) voltage supply terminal (VSWA_P) 376, and a fourth (logic) voltage supply terminal (VSWA_N) 378, a fifth (logic) voltage supply terminal (VSWB_P) 380, and a sixth (logic) voltage supply terminal (VSWB_N) 382. Voltage controller 384 also supplies predetermined voltages VITO_L by voltage supply terminal 396 and VITO_H by voltage supply terminal 397 to ITO voltage multiplexer 399. Voltage multiplexer 399 selects between VITO_L and VITO_H based on control signals received from processing unit 388. Processing unit 388 controls the logic state of (logic) voltage supply terminals VSWA_P 376, VSWA_N 378, VSWB_P 380, and VSWB_N 382 in synchronization with switching of VITO 398 between VITO_L 397 and VITO_H 396. ITO voltage multiplex unit 399 delivers VITO to the transparent common electrode 392, by voltage supply terminal (VITO) 398. Each of the voltage supply terminals V1 372, V0 374, VSWA_P 376, VSWA_N 378, VSWB_P 380, and VSWB_N 382 in FIG. 5 are global signals, wherein each global terminal supplies the same voltage to each pixel cell 305 throughout the entire pixel array at any given instant in the operation of display system 394. VITO 398 asserts a single voltage selected by multiplexer 399 from VITO_L 397 and VITO_H 396 on transparent common electrode 392.
Voltages generated within voltage controller 384 may be generated by the use of digital to analog converters (DAC) and calibrated op-amps, as is well known in the art. Such arrangements create very precise voltages suitable for use in the present application. Such devices are subject to external control by devices such as processing unit 388 by use of voltage set commands which establish a new voltage to be generated by the DAC. A common form of DAC is an rDAC based on the use of a resistor lattice.
FIG. 6A depicts the movement of digital data and digital control signals in a display system. Display system 400 comprises microdisplay controller 420, digital image data input terminal 433, DDR SDRAM (double data rate synchronous dynamic random access memory) 430, memory control interface 431, memory data interface 432, microdisplay 440 and various digital control and data lines (402, 404, 406, 408, 410) that connect microdisplay controller 420 to microdisplay 440. Although DDR SDRAM 430 is preferably a DDR memory with a double data rate interface, other memory devices known in the art may be used. Digital image data input terminal 433 may receive data from a digital input such as HDMI (high definition multimedia interface) or DVI (digital video interface), or may receive input image data from a format converter device operative to receive digital or analog image signal and convert and reformat those signals as is well known in the art.
Image modulation data, whether reformatted or not, is delivered to the microdisplay in a compatible manner for the microdisplay. Those of experience in the art will recognize that the full resolution of the display need not be used for a properly designed microdisplay system. The input image data for each pixel comprises a desired luminance level for that pixel for that image data frame, typically in numerical format. Luminance levels are not absolute but are rather relative to other luminance levels and should be displayed according to the performance characteristics of the display system. A typical luminance level may be defined as representing 8 bit color (256 gray levels) or 10 bit color (1024 gray levels). The number is arbitrary and normally defined by industry standards and display performance characteristics.
Line 402 may comprise a plurality of complementary clock lines. The clock lines allow microdisplay 440 and microdisplay controller 420 to conduct a synchronized transfer of data over a plurality of parallel data transfer lines 410. In one embodiment data transfer lines 410 comprise 64 parallel data lines. In another embodiment data transfer lines 410 comprises 128 parallel data lines. Those of ordinary skill in the art will recognize that the number of parallel data lines may be an arbitrary number and that the maximum number may be dictated by external factors such as the minimum spacing and minimum size of wire bond pads and the space available in which to fabricate said wire bond pads. Line 404 may comprise a set of operation code lines that control the microdisplay 440 and instruct it to handle the data coming over parallel data transfer lines as address information or data information or as some other form of information that may be useful in a practical system. Line 406 may comprise a serial input-output interface. A serial input-output interface may be utilized to transfer control instructions from microdisplay controller 420 to microdisplay 440. Other control functions comprise functions to control other features of microdisplay 440 such as setup configuration. Line 408 may comprise additional features such as control of a temperature measurement sensor (not shown) with bidirectional data flow. A temperature sensor of the type required is disclosed in published patent application US2005/0,052,437, the contents whereof are incorporated into the present application by reference. Other data lines may include such items as a field-invert (FI) signal (not shown) wherein the field-invert signal controls circuitry that triggers a change to the DC balance state of a pixel such as that shown in FIG. 4 by controlling DC balance control element 320 as previously described. Those of ordinary skill in the art will recognize other useful features that may be implemented in an interface between a microdisplay 440 and a microdisplay controller 420. Therefore, the present list is not considered limiting.
FIG. 6B depicts a functional schematic of microdisplay controller 420. Digital data of an image to be displayed is received by terminal 433 on HDMI (High Definition Multimedia Interface) interface 421. Alternatively, the digital data may be received from any industry standard or proprietary digital image interface. The digital data may be received from another device capable of rescaling images or enacting frame rate change or other changes or combination of changes. HDMI interface 422 receives the incoming digital data from a digital video source comprising a pixel clock, horizontal and vertical sync signals, and pixel data for one or more colors. Bit depth may be an industry standard such as 8 bits per color or another arbitrary or emerging standard.
Data received is transferred by logical/serial interface 429 to color shading correction unit 422. Color shading correction unit 422 receives digital input image data and acts upon that data to apply correction factors to the image data such that the hue of the final displayed image is close to the desired color. The origins of color shading errors may originate in a number of causes, including non-uniformities in the display device. A more detailed explanation of color shading correction is found in U.S. Pat. No. 7,129,920 and U.S. Pat. No. 7,990,353, the contents whereof are incorporated into the present patent application by reference. In one embodiment the output data upon which color shading correction unit 422 acts has different bit depth to that of the input data.
Color shading correction unit 422 delivers its output data to look-up table (LUT) unit 423 through logical/serial interface 434. LUT unit 423 acts upon the input data to apply a set of corrections for liquid crystal non-linearity and for other desirable corrections such as for gamma correction, thereby assuring that changes in the image data result in the expected change in the luminance of the image when displayed.
LUT unit 423 delivers its output data to byte-explode unit 424 via logical/serial interface 435. Byte-explode unit 424 acts upon data received from LUT unit 423 to convert the data into a form suitable for display. Byte-explode unit 424 takes the data and expands the number of bits comprising the data. In one instance, byte-explode unit 424 maps the binary data to a larger number of binary weighted and non-binary weighted bits. In one embodiment the non-binary weighted bits comprise a set of “thermometer” or unary (Base 1) bits of higher order than the set of binary weighted bits. In one instance, at least one of the unary bits is of different temporal weighting than the other unary bits. In one embodiment the temporal ordering of the unary bits differs from the order in which the unary bits are activated with increasing gray scale.
The expanded byte count data output of Byte-Explode unit 424 is transferred over logical interface 436 to DDR SDRAM Controller/Interface 425 for transfer to DDR SDRAM 430 (not shown) over memory data interface 432 for buffering. Placement and retrieval of the transferred data is responsive to instructions sent over memory control interface 431. In one example, the expanded byte count data for a row is stored according the temporal order in which the data is to be displayed. In one example, Byte-Explode unit 424 receives data from HDMI Interface 421 and delivers its output to Color Shading Correction unit 422.
The expanded byte count data remains in DDR SDRAM 430 until retrieved by DDR SDRAM controller/Interface 425 over logical interface 432. DDR SDRAM Memory Controller/Interface 425 delivers the retrieved data over logical interface 437 to Bit Plane Scheduler and Sequencer 426.
Bit Plane Scheduler and Sequencer 426 receives expanded byte count data and converts the data into a time ordered sequence of row write events A row write event is the writing of an entire row of the display with binary data corresponding to a modulation state for each pixel on the row. In one instance, the binary data is preceded by data defining the row to which the subsequent data is to be written. The time ordered sequence of row write events is delivered to microdisplay buffer and interface 427 by logical interface 438.
Microdisplay buffer and interface 427 performs actions such as voltage scaling to the signals representing the data for the row write actions to enable it to be electrically transferred to microdisplay 440 over output interface 439. Output interface 439 may be preferably a flexible printed circuit assembly (FPCA) or alternatively may form part of the same printed circuit board as the other components of microdisplay controller 420 or some other form as is known in the art. Output interface 439 comprises a set of parallel lines configured so as to enable the transfer of the row write information to microdisplay 440.
FIG. 6C depicts a functional diagram of the data transfer sections of microdisplay 440. Microdisplay comprises pixel array 441, row decoder left 445, row decoder right 446, column data register array 444, control block 443, and wire bond pad block 442. Wire bond pad block 442 is configured so as to enable contact with an FPCA or other suitable connecting means so as to receive data and control signals over lines from microdisplay controller 420. The data and control signal lines comprise clock signal lines 402, op code signal lines 404, serial input-output signal lines 406, bidirectional temperature signal lines 408, and parallel data signal lines 410.
Wire bond pad block 442 receives image modulation data and control signals and moves these signals to control block 443. Control block 443 receives the image modulation data and routes the image modulation data to column data register array 444. Row address information is routed to row decoder left 445 and to row decoder right 446. In one instance, the value of the Op Code lines 404 determines whether data received on the parallel data signal lines 410 is address information or image data. In one instance, the row address information acts as header, appearing first in time, to be followed by image data for that row.
Row decoder left 445 and row decoder right 446 are configured so as to pull the word line for the decoded row high so that image modulation data for that row may be transferred from column data register array 444 to the storage elements resident in the pixel cells of that row of pixel array 441, as previously described in FIG. 4 and associated text.
One important requirement for any beam steering device is the need to calibrate the performance of the phase-aligned spatial light modulator. FIG. 7A presents Ronchi interferometer 140 comprising coherent light source 142, collimating lens 146, polarizer 148, half wave retarder 150, non-polarizing beam splitter 152, microdisplay 158, polarizer/analyzer 164, focus lens 166, and photometer 170. Coherent light source 142 emits coherent beam of light 144. Collimating lens 146 acts upon coherent beam of light 144 to collimated coherent beam of light 144. Polarizer 148 acts upon coherent beam of light 144 to polarize said beam of light 144. Half wave retarder 150 acts upon coherent beam of light to modify the orientation of the polarization vector of said coherent beam of light 144. Non-polarizing beam splitter 152 acts upon coherent beam of light 144 to pass half of said coherent beam of light 144 to microdisplay 158 and to reflect half of said coherent beam of light 144 to an optical dump (not shown). Microdisplay 158 acts upon coherent beam of light 144 to phase modulate said coherent beam of light with Ronchi phase grating 154. Modulated coherent beam of light 168 is reflected by microdisplay 158 to non-polarizing beam splitter 152. Non polarizing beam splitter 152 acts upon modulated coherent beam of light 168 by reflecting half of said modulated coherent beam of light 168 to analyzer 164 and passing half of said modulated coherent beam of light 168 in a reverse path through half wave retarder 150. Said modulated coherent beam of light 168 is analyzed by polarizer/analyzer 164 and then is focused onto photometer 170 by focus lens 166. Photometer 170 yields first order peak intensity graph 162 when Ronchi phase grating 154 is stepped through a range of phase states.
Ronchi phase grating 154 is further explained in FIG. 7B. Ronchi phase grating 154 comprises a set of stripes in alternating phase states. Stripe 194 represents a first phase state Nref. Phase state Nref corresponds to a reference phase state that remains constant throughout the evaluation of the phase states of microdisplay 158. Stripe 196 represents a second phase state Nv. Phase state Nv is stepped through a range of data states while phase state Nref is held constant. Photometer 170 collects amplitude data regarding the first order diffraction which is then used to estimate the phase state.
Once phase state data is collected for the desired range of values for a phase modulator, this data can be put to use to simplify the construction of specific phase mask configurations on the face of the microdisplay. FIGS. 8A through 8C illustrate a method for using phase data collected to construct a lookup table such that the individual pixels of a phase modulator may be driven to known phase states in order to facilitate creating a desired modulation upon an incident coherent beam of light (not shown.) The details are presented in detail in “Multipoint phase calibration for improved compensation of inherent wavefront distortion in parallel aligned liquid crystal on silicon display,” Oton et al, Applied Optics, Vol. 46, No. 23, pages 5667-5679, Optical Society of America, 2007.
FIG. 8A presents a curve of relative phase (y-axis) as a function of index level. Note that the y-axis of FIG. 8A depicts a total phase modulation range of 3π radians. In most phase modulation applications, the modulation range may be limited to 2π radians since x radians and x+2π radians are considered to be the same in phase space considerations. An alternative name for index level is modulation code. Modulation codes are often developed for use in conjunction with specific hardware implementations, and may represent a variety of differing conditions. No industry standard exists and each manufacturer typically develops a proprietary version based on its own hardware.
FIG. 8B depicts a mapping between an 8 bit gray level range (0 to 255) and a subset of the index levels of FIG. 8A. In this example the range of index levels from 200 to 680 was selected because it covers the required 2π radians of phase modulation and because it is the most linear portion of the mapping of FIG. 8A.
The number of points in the selected range of the index level is 480, which offers the choice of those 480 points to make the final range of phase modulation steps generated by the mapped gray level range of 0 to 255 linear. FIG. 8C depicts the final range of phase modulation steps relative to gray levels, and by inspection the result is substantially linear.
Digital pulse width modulated displays offer several advantages over analog driven displays. First, it is possible to control time more precisely than voltage which offers better control over phase steps. Second, the pixel voltage can be constantly supplied and does not rely upon a capacitive element in the pixel to hold the charge. Third, it is less prone to be affected by high light loads. Applicant has developed hardware and software to enable application of its pulse width modulation methods to the task of pulse width modulating a phase aligned spatial light modulator.